1. Field of the Invention
The present invention relates to a semiconductor device comprising a polycide structure composed of a polysilicon layer and a silicide layer, in which both p-type regions and n-type regions are present in the polysilicon layer in a mixed condition, and a method for fabricating such a semiconductor device.
2. Description of the Prior Art
In recent years, it has been known that, in order to reduce the size of an MOS transistor, it is advantageous to use p.sup.+ -type polysilicon for the gate electrode of a p-channel MOS transistor and n.sup.+ -type polysilicon for the gate electrode of an n-channel MOS transistor. This technique is described, for example, in IEEE, IEDM, Technical Digest, pp. 418-422 (1984).
Also, p.sup.+ -type polysilicon is used for a polysilicon layer so as to contact with a p.sup.+ -type region formed in a semiconductor substrate, and n.sup.+ -type polysilicon is used for a polysilicon layer so as to contact with an n.sup.+ -type region formed in the semiconductor substrate. Therefore, in a CMOS semiconductor device in which both p-channel and n-channel MOS transistors are formed on one semiconductor substrate, it is advantageous to form both p.sup.+ -type regions and n.sup.+ -type regions in one polysilicon layer in a mixed condition, in order to reduce the size of an integrated circuit device as well as other purposes.
The polysilicon layer in which p.sup.+ -type regions and n.sup.+ -type regions are present in a mixed condition has a high specific resistance compared with that of a general metal layer. For this reason, it is a general practice to deposit on the polysilicon layer a metal silicide layer having a comparatively low specific resistance and a high melting point, so as to form a polycide film. In this two-layer polycide film, the p.sup.+ -type regions and the n.sup.+ -type regions of the polysilicon layer can electrically communicate with each other through the metal silicide layer formed on the polysilicon layer, thereby eliminating the necessity of an additional contact area for the connection between the p.sup.+ -type regions and the n.sup.+ -type regions. Further, since all materials constituting the polycide film have a high melting point of no less than 1000.degree. C., the polycide film can be subjected to heat treatment at 900.degree. C. so as to be planarized using a BPSG film (silicate glass containing boron and phosphorus). This type of semiconductor device is disclosed, for example, in Japanese Laid-Open Patent Publication No. 57-192079.
However, in the polycide film formed by simply depositing silicide on the polysilicon layer, when it is subjected to heat treatment in a post-process such as the planarization using the BPSG film, boron, which is a p-type impurity contained in the p.sup.+ -type region of the polysilicon layer, and phosphorous or arsenic, which is an n-type impurity contained in the n.sup.+ -type region thereof, diffuse into the silicide layer and become mixed with each other. This causes a problem of an unstabilized threshold voltage (Vt) when the polycide film is used for a gate electrode of a p-channel MOSFET, though this does not occur for an n-channel MOSFET. This problem is described, for example, in IEEE, Electron Device Letter, vol. 12, pp. 696-698, 1991. Another problem is that the contact resistance of the polycide film increases when it is used for the interconnection between an n.sup.+ -type diffusion layer and a p.sup.+ -type diffusion layer.
In order to prevent the diffusion of the impurities into the silicide layer, a technique of forming a diffusion barrier made of titanium nitride (TiN), for example, between the polysilicon layer and the silicide layer has been disclosed, for example, in Japanese Laid-Open Patent Publications No. 1-265542 and No. 2-192161.
However, the effect of the TiN film as the diffusion barrier is not stable because it varies depending on process parameters such as the composition ratio of N/Ti, the amount of oxygen contained as an impurity, the grain size, and the crystal orientation. In particular, when the polycide film is sued for interconnections, the thickness of the TiN film is reduced at the contact areas, and thus the effect of the diffusion barrier is lost. Consequently, p-type impurities and n-type impurities contained in the polysilicon layer diffuse into the silicide layer, and through the silicide layer, the p-type impurities reach the n.sup.+ -type polysilicon region and the p-type impurities reach the p.sup.+ -type polysilicon region. As a result, the concentration of electric carriers is lowered due to the compensation effect, which in turn causes the problem of increased contact resistance.